The questions engineers actually ask.
Is this another LLM that draws schematics?
No, and that's the entire point. The model never writes a KiCad file, never holds the design in its head, and never recalls an engineering rule from memory. It proposes small typed changes. Deterministic code wires, derives, computes and compiles.
Do I own the output?
Yes, unconditionally. Schematic, project, netlist and BOM in KiCad's own formats. Export is always ungated — never behind a plan, a trial or a lock. No proprietary format sits between you and your board.
Does it lay out the PCB?
Not yet. Today it stops at the schematic and project. The next step writes layout constraints — net classes, impedance targets, length-match groups — into the KiCad project so you inherit them when you route by hand. Routing with KiCad's design-rule check in the loop comes after that.
What happens if the catalog doesn't have my part?
Two answers. Short term, name it on the waitlist and it goes to the front of the verification queue — verification is demand-driven. Longer term, you bring your own record: the format is the contract, and yours is linted and validated exactly as ours is.
How do I know a number wasn't hallucinated?
Because every field carries a provenance tag, and every finding lists the unverified inputs it consumed. If a value came from a model reading a datasheet rather than a person, the dossier says llm_extracted next to it — and the report's overall trust degrades automatically. We'd rather show you a weak number honestly than a strong one you can't check.
Will it design my battery charger?
It will run every deterministic check it has — programming resistor, thermal at input maximum, connector polarity — and then stop and require a human. Battery charging, mains and motor drive always end in review, with the checks that ran listed. That never gets softened.
Will it invent a circuit I've never seen?
No. It composes catalog parts, interface definitions and proven sub-circuits whose claims the engine checks against the derived nets — never the sub-circuit's own word. It will not invent an analog front end, and it doesn't pretend to.
Can I edit the design and keep the edits?
Yes. Edits are small, typed and guarded by a revision check, so what you fixed stays fixed. Whole-design regeneration is impossible by construction — the agent has no path to it. Every batch is followed by a full re-validation.
Which boards is it good at today?
ESP32-class boards: an MCU or module, sensors on I²C or SPI, a GPS or radio on UART, an LDO or charger, a battery. Boards with DDR, PCIe or HDMI are explicitly out of scope until the layout data and vendor reference designs exist.
When can I use it?
The engine and CLI work today. The browser workspace and private alpha are what we are building now, and seats open in small batches as the catalog grows. If you want to be in the first batch — or to be a design partner and pick the target board — the waitlist is open, and email reaches me directly.
Question we didn't answer?
Ask it directly. I reply, not a form.